1. Field of the Invention
The present invention relates generally to data communications and more specifically to testing data communications equipment.
2. Background Art
A data communication network includes multiple communication devices and a physical layer device or medium for interconnecting or networking the communication devices. The communication devices may include stand-alone computers or embedded controllers. Often, the communication devices include or connect with high-speed analog serial data interfaces or ports configured to operate at sub-Gigabit (e.g., USB 2.0 at 480 Mbps) or Gigabit-per-second (Gbps) data rates. Typically, the serial data interfaces are configured in accordance with known data transmission standards, such as optical fiber and copper wire Ethernet standards. A physical layer device interfaces with such high-speed analog serial data links. It is desirable that the physical layer device be capable of operating at the Gigabit-per-second data rates, and in accordance with the different transmission standards.
To accommodate such data rates and standards, a physical layer device may contain, among other devices, a serializer/deserializer (SERDES) device. A SERDES device may include a high speed serial transceiver. Such transceivers contain embedded clocks and circuits designed for clock and data recovery (CDR). These CDR circuits present a challenge for high volume production testing using automated test equipment (ATE). In order to identify devices with faults in their CDR circuits, it is desirable that the ATE generate a sufficiently high speed serial data stream that varies in frequency or is otherwise offset from the embedded reference clock. Because the typical ATE cannot provide such a frequency varying data stream, alternative test techniques must be used to mimic these signals. Such techniques are costly, and involve compromises which result in less than complete fault coverage.
Typical solutions to this problem involve either adding circuitry to the device (e.g., adding an additional phase locked loop (PLL) and clock circuitry), or making use of certain test techniques such as using a high speed analog clock to mimic a 1010 . . . 1 data stream. Also, because these high speed transceivers often make use of the latest process technologies, it can be very difficult for ATE vendors to supply test equipment that is effective at ever higher frequencies and changing standards. Therefore, there is a need for a simpler and more cost effective method of generating a high speed serial data stream that varies in frequency or is otherwise offset from the embedded reference clock.